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HB52D48GB-F
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Description Features
32 MB Unbuffered SDRAM Micro DIMM 4-Mword x 64-bit, 100 MHz Memory Bus, 1-Bank Module (4 pcs of 4 M x 16 components) PC100 SDRAM
E0011H10 (1st edition) (Previous ADE-203-1149A (Z)) Jan. 19, 2001
The HB 52D48GB is a 4M x 64 x 1 banks S ynchronous Dyna mic R AM Micro Dua l In- line Memory Module (Micro DIMM), mounted 4 pieces of 64-Mbit SDRAM (HM5264165FTT) sealed in TSOP package and 1 piece of ser ia l EEP RO M (2- kbit EEP RO M) for P rese nce De te ct (P D). An outline of the produc t is 144-pin Zig Za g Dua l tabs socke t type compa ct and thin pac kage . The ref ore, it make s high density mounting possible without surf ace mount tec hnology. It provide s common data inputs and outputs. De coupling ca pac itor s ar e mounted beside TSOP on the module board.
* 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 38.00 mm (Length) x 30.00 mm (Height) x 3.80 mm (Thickness) Lead pitch: 0.50 mm * 3.3 V power supply * Clock frequency: 100 MHz (max) * LVTTL interface * Data bus width: x 64 Non parity * Single pulsed RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length : 1/2/4/8/full page * 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) interleave (BL = 1/2/4/8)
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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This Product became EOL in October, 2005.
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HB52D48GB-F
* Programmable CE latency : 2/3 (HB52D48GB-A6F/A6FL) : 3 (HB52D48GB-B6F/B6FL) * Byte control by DQMB * Refresh cycles: 4096 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh * Low self refresh current: HB52D48GB-A6FL/B6FL (L-version) * Full page burst length capability Sequential burst Burst stop capability
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Ordering Information
Type No. HB52D48GB-A6F HB52D48GB-B6F HB52D48GB-A6FL HB52D48GB-B6FL 100 100 100 100 MHz MHz MHz MHz
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Frequency 2/3 3 2/3 3 1pin 2pin
CE latency
Package Micro DIMM (144-pin)
Contact pad Gold
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Front Side Back Side Data Sheet E0011H10
Pin Arrangement
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143pin 144pin
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HB52D48GB-F
Front side Pin No. 1 3 5 7 9 Signal name Pin No. VSS 73 Back side Signal name Pin No. NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 Signal name Pin No. VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VCC A3 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Signal name CK1 VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 A13 (BA0) VSS A12 (BA1) A11 VCC
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DQ0 DQ1 DQ2 DQ3 VCC 75 77 79 81 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 83 DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131
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DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10 (AP) VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28
Data Sheet E0011H10 3
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30 32 34 A4 A5 36 VSS 38 DQ40 40 DQ41 42 44 DQ42 DQ43 VCC 46 48 50 52 54 DQ44 DQ45 DQ46 DQ47 VSS 56 58 60 NC NC
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114 116 DQMB6 118 DQMB7 120 VSS 122 124 126 DQ56 DQ57 DQ58 128 DQ59 130 VCC 132 DQ60
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HB52D48GB-F
Front side Pin No. 61 63 65 67 69 71 Signal name Pin No. CK0 VCC 133 Back side Signal name Pin No. DQ29 DQ30 DQ31 VSS SDA VCC 62 64 66 68 70 72 Signal name Pin No. CKE0 VCC CE NC NC NC 134 136 138 140 142 144 Signal name DQ61 DQ62 DQ63 VSS SCL VCC
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135 RE W S0 137 139 141 143 NC
Pin Description
Pin name A0 to A11
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Function Row address A0 to A11 Column address A0 to A7 BA1, BA0
Address input
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Bank select address Data-input/output Chip select Column address asserted Write enable Byte input/output mask Clock input Clock enable Clock input for serial PD Power supply Ground No connection Data Sheet E0011H10
A12/A13 DQ0 to DQ63 S0 RE CE W DQMB0 to DQMB7 CK0/CK1 CKE0 SDA SCL VCC VSS NC
Row address asserted bank enable
Data-input/output for serial PD
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HB52D48GB-F
Serial PD Matrix*1
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Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Number of banks Module data width SDRAM cycle time (highest CE latency) 10 ns 10 11 12 Module configuration type Refresh rate/type 13 14 15 SDRAM width 16 17 SDRAM device attributes: Burst lengths supported 18 19 SDRAM device attributes: CE latency SDRAM device attributes: S latency
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 80 08 04 0C 08 01 40 00 01 A0 128 256 byte SDRAM 12 8 1 64 0 (+) LVTTL CL = 3
Number of row addresses bits 0 Number of column addresses bits 0 0 0
Module data width (continued) 0 Module interface signal levels 0 1
SDRAM access from Clock (highest CE latency) 6 ns
Error checking SDRAM width
0 SDRAM device attributes: minimum clock delay for backto-back random column addresses 1 0
SDRAM device attributes: number of banks on SDRAM device
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0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Sheet E0011H10 5
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1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0
0
0
60
0 0
0 0
00 80
Non parity Normal (15.625 s) Self refresh 4M x 16 --
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0 0 0 0 10 00 0 1 01 1 CLK 1 0 1 0 8F 04 1, 2, 4, 8, full page 4 1 0 0 1 06 01 2, 3 0
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Byte No. Function described 20 21 22 23 SDRAM device attributes: W latency Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 01 00 0E A0 0 Unbuffer VCC 10% CL = 2
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SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-A6F/A6FL) 10 ns (-B6F/B6FL) 15 ns 24 (-B6F/B6FL) 8 ns 25 SDRAM cycle time (3rd highest CE latency) Undefined 26 27 28 29 30 31 32 33 34 35 RE to CE delay min Minimum RE pulse width Density of each bank on module 36 to 61 Superset information 62 63 SPD data revision code (-B6F/B6FL) 64 72 Manufacturing location 6
SDRAM module attributes
1 0
1 1
1 1
1 0
0 0
0 0
0 0
0 0
F0 60
SDRAM access from Clock (2nd highest CE latency) (-A6F/A6FL) 6 ns
SDRAM access from Clock (3rd 0 highest CE latency) Undefined Minimum row precharge time Row active to row active min
Address and command signal 0 input setup time Address and command signal 0 input hold time Data signal input setup time Data signal input hold time 0 0 0 0 0 0
Checksum for bytes 0 to 62 (-A6F/A6FL)
Manuf act urer's J EDEC I D c ode 0 x
65 to 71 Manuf act urer's J EDEC I D c ode 0
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1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x
0 0
0 0
0 0
0 0
0 0
0 0
80 00
0
0
0
0
0
0
00
Data Sheet E0011H10
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0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 0 1 0 0 0 0 1 0 0 x 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 x 0 0 x 1 0 x
0 0
0 0 0 0 0 0 0
14 14 14 32 08 20 10
20 ns 20 ns 20 ns 50 ns 32M byte
0 1 0 0 0
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2 ns 1 ns 0 0 0 1 0 0 0 0 20 10 00 12 2 ns 1 ns Future use Rev. 1.2A 0 0 04 4 0 0 74 116 1 0 x 1 0 x 07 00 xx HITACHI * 3 (ASCII-8bit code)
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Byte No. Function described 73 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-A6F/A6FL) (-B6F/B6FL) 84 85 86 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 x x 48 42 35 32 44 34 38 47 42 2D 41 42 36 46 4C 20 20 20 20 20 30 20 xx xx H B 5 2 D 4 8 G B -- A B 6 F L (Space) (Space) (Space) (Space) (Space) Initial
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74 75 76 77 78 79 80 81 82 83 87 88 89 90 91 92 93 94 Revision code Revision code Manufacturing date Manufacturing date 95 to 98 Assembly serial number 126 127 (-B6F/B6FL)
Manufacturer's part number Manufacturer's part number Manufacturer's part number (L-version) Manufacturer's part number
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number
99 t o 125 Manufacturer specific data Intel specification frequency
Intel specification CE# latency 1 support (-A6F/A6FL) 1
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0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 x x *6 -- 0 -- 1 1 0 0 0 0 0 0 x x 1
Data Sheet E0011H10 7
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0 0 1 1 1 0 0 0 1 1 1 1 1 1 x x 0 0 0 0 1 0 x x 0 0 0 0 0 0 x x 0 0 0 0 0 0 x x -- 1 0 -- 0 -- 0 -- 1 0 0 1 0 0 0 1
0 0 0 0 0 0 0 0 x x
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(Space) Year code (BCD)*4 Week code (BCD)*4 -- 0 -- 0 -- *5 64 100 MHz 1 1 C7 CL = 2, 3 0 1 C5 CL = 3
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Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Intel specification (Rev.1.2A). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary Coded Decimal". 5. All bits of 99 through 125 are not defined ("1" or "0"). 6. Bytes 95 through 98 are assembly serial number.
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Data Sheet E0011H10
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HB52D48GB-F
Block Diagram
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S0 W DQMB0 DQ0 to DQ7 DQMB1 DQ8 to DQ15 DQMB2 DQ16 to DQ23 DQMB3 DQ24 to DQ31 RE CE A0 to A11 BA0 BA1 CKE0 CK0 R0 CK1 VCC
C0-C7
CS
DQMB4 8 N8, N9 DQ32 to DQ39
CS
8 N0, N1
D0
DQMB5 8 N10, N11 DQ40 to DQ47 CS CS 8 N12, N13 DQ48 to DQ55
D2
8 N2, N3
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8 N4, N5 8 N6, N7 CLK (D0) CLK (D1) CLK (D2) CLK (D3) C200
C100-C103
DQMB6
D1
DQMB7 8 N14, N15 DQ56 to DQ63
D3
RAS (D0 to D3) CAS (D0 to D3)
A0 to A11 (D0 to D3) A13 (D0 to D3) A12 (D0 to D3) CKE (D0 to D3)
VCC (D0 to D3, U0) VSS (D0 to D3, U0)
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SCL
Serial PD SCL A0 A1 A2 U0 SDA SDA
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VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D3: HM5264165 U0: 2-kbit EEPROM C0 to C7: 0.33 F C100 to C103: 0.1 F C200: 10 pF N0 to N15: Network resistors (10 ) R0: Resistor (10 )
VSS
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Data Sheet E0011H10 9
HB52D48GB-F
Absolute Maximum Ratings
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Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to VSS . Parameter Supply voltage VCC VSS Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. 6. VIH VIL 10
Symbol VT VCC Iout PT Topr Tstg
Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 4.0 0 to +65 -55 to +125
Unit V V mA W C C
Note 1 1
DC Operating Conditions (Ta = 0 to +65C)
Symbol Min 3.0 0 Max 3.6 0 Unit V V V V Notes 1, 2 3 1, 4, 5 1, 6
All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width 5 ns at VCC. Others: VIH (max) = 4.6 V for pulse width 5 ns at VCC. VIL (min) = -1.0 V for pulse width 5 ns at VSS .
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Data Sheet E0011H10
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2.0 -0.3 0.8
VCC + 0.3
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HB52D48GB-F
VIL/VIH Clamp (Component characteristic)
I (mA)
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Minimum VIL Clamp Current
VIL (V) -2 -1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0 0 -5 -10 -15 -20 -25 -30 -35 -2
This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins.
I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0
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-1.5
Data Sheet E0011H10 11
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0 0 0 -1 VIL (V)
-0.5
0
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Minimum VIH Clamp Current
I (mA)
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VIH (V) VCC + 2 VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1 VCC + 0.8 VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0 10 8 6 4 2 0 VCC + 0
I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0
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VCC + 0.5
Data Sheet E0011H10 12
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VCC + 1
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VCC + 1.5 VCC + 2 VIH (V)
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IOL/IOH Characteristics (Component characteristic)
IOL (mA)
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Output Low Current (I OL)
Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 50 0 0 0.5
I OL
I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
Min (mA) 0 27 41 51 58 70 72 75 77 77 80 81
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1 1.5 2 2.5 Vout (V) Data Sheet E0011H10
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min max 3 3.5
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HB52D48GB-F
Output High Current (I OH ) (Ta = 0 to 65C, VCC = 3.0 V to 3.45 V, VSS = 0 V)
IOH (mA)
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Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 0 0 0.5 -100 -200 -300 -400 -500 -600 14
I OH
I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
Min (mA) -- --
0 -21 -34 -59
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-67 -73 -78 -81 -89 -93 1 1.5 2 2.5 Vout (V) Data Sheet E0011H10
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min max
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DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
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Parameter Operating current I CC1 Standby current in non power down Active standby current in non power down Burst operating current Refresh current Self refresh current Self refresh current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage I CC4 I CC5 I CC6 I CC6 I LI I LO VOH VOL
HB52D48GB -A6F/B6F/A6FL/B6FL Max 260 6 4 40 16 72 260 440 4 Unit mA mA mA mA mA mA mA mA Test conditions Burst length = 1 t RC = min CKE0 = VIL, t CK = CKE0, S = VIH, t CK = 12 ns CKE0, S = VIH, t CK = 12 ns CKE0, S = VIH, t CK = 12 ns t CK = 12 ns, BL = 4 t RC = min VIH VCC - 0.2 V VIL 0.2 V Notes 1, 2, 3
Symbol Min -- -- -- -- -- -- -- -- -- --
Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) I CC2N
CKE0 = VIL, t CK = 12 ns 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 3 8
Active standby current in power I CC3P down
Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current.
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I CC3N -10 -10 2.4 --
Data Sheet E0011H10 15
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mA 2.2 10 10 mA A A -- V V 0.4
0 Vin VCC
0 Vout VCC DQ = disable
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I OH = -4 mA I OL = 4 mA
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Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
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Parameter Input capacitance (Address) Input capacitance (S0) Notes: 1. 2. 3. 4. 16
Symbol CIN CIN CIN CIN CI/O
Max 40 40 40 20 20
Unit pF pF pF pF pF
Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Input capacitance (RE, CE, W, CK0/CK1, CKE0)
Input capacitance (DQMB0 to DQMB7) Input/Output capacitance (DQ0 to DQ63)
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
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Data Sheet E0011H10
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HB52D48GB-F
AC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
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Parameter System clock cycle time (CE latency = 2) (CE latency = 3) t CK t CK CK high pulse width CK low pulse width t CKH t CKL Access time from CK (CE latency = 2) (CE latency = 3) Data-out hold time t AC t AC t OH CK to Data-out low impedance t LZ CK to Data-out high impedance t HZ Data-in setup time Data-in hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise and fall) Refresh period t RC t RAS t RP t DPL tT t REF
HB52D48GB -A6F/A6FL Max -- -- -- -- 6 6 -- -- 6 -B6F/B6FL Min 15 10 3 3 -- -- 3 2 -- Max -- -- -- -- 8 6 -- -- 6 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1, 5, 6 1 1, 5 1 1 1 1, 2 Notes 1
PC100 Symbol Symbol Min Tclk Tclk Tch Tcl 10 10 3 3 -- -- 3 2 --
CKE setup time for power down t CESP exit
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Tac Tac Toh t AS , t CS, t DS, t CES Tsi Tpde Thi t AH, t CH, t DH, t CEH Trc Tras Trcd Trp Tdpl Trrd t RCD t RRD
Data Sheet E0011H10 17
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2 -- 2 2 -- 2 1 -- -- 1 70 50 20 20 10 20 1 -- 70 120000 -- -- -- 50 20 20 10 -- 5 20 1 64 --
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120000 ns 1 -- -- -- ns ns ns 1 1 1 -- 5 ns 1 ns 64 ms
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HB52D48GB-F
Notes: 1. 2. 3. 4. 5. 6. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CK rising edge except power down exit command. t AS /tAH: Address, t CS/tCH: S, RE, CE, W, DQMB t DS/tDH: Data-in, t CES/tCEH : CKE
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Test Conditions
2.4 V 0.4 V
* Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
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2.0 V 0.8 V t
T
input
I/O CL
Data Sheet E0011H10 18
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HB52D48GB-F
Relationship Between Frequency and Minimum Latency
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Parameter Frequency (MHz) tCK (ns) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input (CE latency = 3) Last data out to active command (auto precharge) (same bank) (CE latency = 3) Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command
HB52D48GB -A6F/A6FL/B6F/B6FL 100 Symbol lRCD lRC lRAS lRP lDPL lRRD Tdpl PC100 Symbol 10 2 7 5 2 1 2 Notes 1 = [lRAS+ lRP] 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank)
Precharge command to high impedance (CE latency = 2)
Last data out to precharge (early precharge) (CE latency = 2)
Column command to column command
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Data Sheet E0011H10 19
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lSREX Tsrx 1 lAPW lSEC Tdal 4 7 lHZP lHZP lAPR Troh Troh 2 3 1 lEP lEP lCCD lWCD lDID lDOD lCLE lRSA -1 -2 1 Tccd Tdwd 0 0 2 Tdqm Tdqz Tcke 1 Tmrd 1
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HB52D48GB-F
HB52D48GB Parameter -A6F/A6FL/B6F/B6FL 100 Symbol lCDD lPEC lBSR lBSR lBSH lBSH lBSW PC100 Symbol 10 0 1 1 2 2 3 0 Notes
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Frequency (MHz) tCK (ns) S to command disable Power down exit to command input Burst stop to output valid data hold (CE latency = 2) (CE latency = 3) (CE latency = 3) Burst stop to write data ignore 20
Burst stop to output high impedance (CE latency = 2)
Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP].
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Data Sheet E0011H10
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HB52D48GB-F
Pin Functions
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Detailed Operation Part
CK0/CK1 (in pu t p in ): C K is the master cloc k input to this pin. The other input signals ar e re fe rre d at C K rising edge. S 0 (in pu t p in ): Whe n S is Low, the command input cyc le bec omes valid. Whe n S is High, all inputs ar e ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or wr ite command cyc le C K rising edge . And this column addr ess bec omes burst ac ce ss start addr ess. A10 def ines the pre cha rge mode. Whe n A10 = High at the pre cha rge command cyc le, both banks ar e pre cha rged. B ut whe n A10 = Low at the pre cha rge command cyc le, only the bank that is sele cted by A12/A13 (B A) is precharged. A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3 is selected. CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQMB 0 to DQMB 7 (in pu t p in s): R ea d oper ation: If DQMB is High, the output buff er bec omes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Wr ite oper ation: If DQMB is High, the pre vious data is held (the new data is not wr itten) . If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
Refer to the HM5264165F/HM5264805F/HM5264405F-75/A60/B60 datasheet.
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Data Sheet E0011H10 21
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HB52D48GB-F
Physical Outline
15.0
1
A
17.625
B 0.875
2.5 Min
3.5 Min
35.50 37.0 0.08 35.50
17.875
0.625
R1.0 0.1
2
1.0 Min
Detail A
Detail B
4.0 0.1
4-R1.0 0.1
;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;; (back) ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;
1.0 Min
3.5 Min 0.80 0.08 0.50
5.0 0.1
0.25 Max
0.37 0.03
1.0 0.08
Data Sheet E0011H10 22
2.00 Min
EO
1.0 Min 30.0
42.0 Max (38.0) 1.0 Min
Unit: mm 3.80 Max
;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;; (front) ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;
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HB52D48GB-F
Cautions
EO
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
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Data Sheet E0011H10 23
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